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  • Analysis
  • Compiler
  • Design
  • FPGA
  • Physical Design
  • Rtl
  • Verilog
  • VHDL
  • VLSI


  • Integrated Circuit Design

    $15/hr Starting at $25 Ongoing

    Dedicated Resource

    I am a vlsi design engineer,with experience in ASIC/FPGA designs using VHDL and verilog. I have done projects which require the entire RTL-to-netlist flow and also have done projects from netlist-to-GDSII...

    AnalysisCompilerDesignFPGAPhysical Design

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