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Engineering & Architecture

Integrated Circuit Design

I am a vlsi design engineer,with experience in ASIC/FPGA designs using VHDL and verilog. I have done projects which require the entire RTL-to-netlist flow and also have done projects from netlist-to-GDSII flow. I have expertise in verilog,vhdl and have experience in using SoC encounter, a physical design tool.

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$15/hr Ongoing

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I am a vlsi design engineer,with experience in ASIC/FPGA designs using VHDL and verilog. I have done projects which require the entire RTL-to-netlist flow and also have done projects from netlist-to-GDSII flow. I have expertise in verilog,vhdl and have experience in using SoC encounter, a physical design tool.

Skills & Expertise

AnalysisCompilerDesignFPGAPhysical DesignRtlVerilogVHDLVLSI

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