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Engineering & Architecture engineering (mechanical / chemical / civil / electrical)

Digital Design Engineer, ASIC, FPGA

$20/hr Starting at $25

Digital Front-End Designing.

Write RTL in verilog, verification.


Work: Have 8+ years experience in Digital Design.

Education: MSC and BSC of VLSI design



design/architecture development per specification. RTL coding in verilog/SystemVerilog, constraints, STA, verilog based test environment, FPGA validation.


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$20/hr Ongoing

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Digital Front-End Designing.

Write RTL in verilog, verification.


Work: Have 8+ years experience in Digital Design.

Education: MSC and BSC of VLSI design



design/architecture development per specification. RTL coding in verilog/SystemVerilog, constraints, STA, verilog based test environment, FPGA validation.

Skills & Expertise

DesignDigital DesignEducationEngineeringFPGARtlVerilogVLSI

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