FPGA/ASIC Design Engineer with 6 yr exp (3655694)

Engineering & Architecture

FPGA/ASIC Design Engineer with 6 yr exp

$30/hr Starting at $25

I have worked with various companies in Pune and Bangalore for 6 years. I have expertise in VHDL and verilog both. I have experience in IP development for memories and JEDEC protocol with ASIC tool chain. I am having good experience in image processing algorithm developments on FPGA and testing the same.

About

$30/hr Ongoing

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I have worked with various companies in Pune and Bangalore for 6 years. I have expertise in VHDL and verilog both. I have experience in IP development for memories and JEDEC protocol with ASIC tool chain. I am having good experience in image processing algorithm developments on FPGA and testing the same.

Skills & Expertise

DesignFPGAImage ProcessingProcessingTestingVerilogVHDL

Rohini P