I have more than 7 years of experience in RTL design and verification and worked on various projects on both FPGA and ASIC platforms. I have been consulting graduate and undergraduate students online from various countries to complete their assignments/projects. Here are my areas of interest. 1. RTL design and verification (Both FPGA and ASIC) 2. Teaching programming languages like verilog, System verilog and FPGA basics 3. SOC based projects