• A dedicated professional with 3.10 years of experience in Custom Layout Design. • Worked on Samsung 7nm, 5nm, 4nm, 55nm, 130nm and Intel 10nm technology process nodes. • Expertise executing physical verification in the form of DRC, LVS. • Experience in handling Analog Layout Designs like various blocks like Level Shifter, Band Gap Reference, PLL sub blocks, Global distributor and Standard Cells. • Familiar with Layout Techniques and Design Rules. • Creating Guard Rings for devices and providing shielding for critical signals. • Experience in Matching Techniques like Common-centroid and Interdigitization. • Taking care of Electro migration.