My Self Mohit L. I completed B.E in Electronics & Communication in 2016 and then M-Tech in VLSI design in 2019. I have work experience in Cadence Virtuoso, Mentor Graphics Pyxis and Calibre, Microwind, PSpice, LTSpice, KiCAD, OrCAD, Eagle and Altium tools for Circuit Design/PCB Design, Layout, DRC and LVS. I have work experience in MS-Office from last 10 year. I have work experience in data entry, data research analysis and typing, online data entry, google spreadsheet, email writing, data transcription, report writing.
I proposed a sub threshold digital logic circuit using mux with forward body biasing to reduce the critical path delay and energy consumption. The proposed circuit is applied to the longest delay path of the 64-bit ripple carry adder operated at subthreshold region. Here proposed circuit with 64-bit ripple carry adder is implemented using Cadence Virtuoso at 45 nm technology and compared with the circuit studied from literature survey and published paper on that project in IEEE Xplore.