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Dr., Chip Design Expert

A highly qualified, dedicated and driven semiconductor device engineer and scientist with extensive project management and device engineering experience. Technology interface to GLOBALFOUNDRIES (65G), TSMC (65LP, 40LP) Implemented Projects: Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110) Trench Gate with Carrier Storage (CS) layer IGBT simulation and optimization. ChemFET and enzyme - protein sensitive FET Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K. MOS controlled thyristor (2500V, 50 A) Press Pack HV-IGBT (4500V, 40–1000A) Solar Cells made with multisilicon wafers, 11.5% efficiency Avalanche Photodiode simulation (3D Single Event Upset) and optimization Semiconductor device models implemented with VHDL simulator SJ MOSFET Devices (CoolMOS), special development – SJ MOSFET Avalanche Ruggedness, various die edge termination structures. Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization

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$12/hr Ongoing

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A highly qualified, dedicated and driven semiconductor device engineer and scientist with extensive project management and device engineering experience. Technology interface to GLOBALFOUNDRIES (65G), TSMC (65LP, 40LP) Implemented Projects: Humidity Sensor (Integrated Capacitor), Pressure Sensor (Bulk Silicon orientation (110) Trench Gate with Carrier Storage (CS) layer IGBT simulation and optimization. ChemFET and enzyme - protein sensitive FET Design and manufacturing BIB (Blocked Impurity Band) Photodetector for the 12-16 micron wavelength, 64x64 array, flip chip mounting with multiplexor, cooled T=10 K. MOS controlled thyristor (2500V, 50 A) Press Pack HV-IGBT (4500V, 40–1000A) Solar Cells made with multisilicon wafers, 11.5% efficiency Avalanche Photodiode simulation (3D Single Event Upset) and optimization Semiconductor device models implemented with VHDL simulator SJ MOSFET Devices (CoolMOS), special development – SJ MOSFET Avalanche Ruggedness, various die edge termination structures. Junction Termination Extension Variation Lateral Doping (JTE VLD), own theoretical results in design optimization

Skills & Expertise

DesignElectronicsEngineeringGdsLayout DesignProduct EngineeringProject ManagementSemiconductorSemiconductor IndustryVHDL

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