I have done tremendous amount of work on Verilog HDL and FPGAs. My Masters thesis is on optimization and performance evaluation of ECC algorithms in Verilog and synthesize on various FPGA devices (Virtex,4,5,6,7 and Artix & families). Moreover i am very good with electrical circuits and programming languages like C, C++ and python.
I have an extensive research experience in embedded systems design and their verification at higher abstraction level. We modeled various embedded systems like UAV, Air traffic control, car collision avoidance system in UML. Afterwards, a transformation engine was developed transformation which takes UML model as input and generates its system verilog model. For verification purposes we provided SVOCL library at higher abstraction level extended from OCL to write assertions for verification purposes.
I have worked on machine learning in python Tensor flow and have a pretty good knowledge of machine learning algorithms like SVMs, ANNs etc.
I have co-authored 3 journals and 6 conference publications and few are in the pipeline as well, so i have sound technical writing skills as well.