UPLINK ARRAY – DEEP SPACE NETWORK 2014 - 2016 COMMON PLATFORM ALGORITHMS 2008 - 2015 ? FPGA lead designer responsible for the implementation of a >600Msps receiver, Viterbi & Reed Solomon decoder ? Design is implemented as parallel DSP processing channels and consists of a DMA interface for telemetry data through a PCIe interface. Originally implemented with a dual 10GbE UDP interface for engineering and test data ? Implemented and tested the design during development on a variety of FPGA’s: Virtex 2-7, UltraScale & Zynq