I am a Senior Electrical engineer with over 10 years of experience in the field. The focus of my work as been in FPGA design and architecture. I am very familiar with all aspects of the digital design flow including high level architecture, modular design, synthesis, place and route, simulation, debug, and verification. I am fluent with the two most common HDL languages - VHDL and Verilog. I have worked on many complicated design issues such as clock-crossing, high speed I/O, DSPs, Software registers R/W Access, and meta-stability. I have also worked through synthesis / place and route issues such as LUT / BRAM utilization, routing constraints, MMCM clocking, and timing optimization Beyond the FPGA world I also have experience in both PCB schematic design and layout. I worked on several high speed I/O designs included USB 3.1 and PCIE gen3/4. Each of those designs were modular and included multiple power rails/planes as well as PLDs, FPGAs, and microprocessors.