Serhiy Drashpul

Chernihiv, Chernihivs'ka Oblast', Ukraine

Yearly Stats: $0 Earned |

Hardware design engineer, FPGA/PLD/ASIC

CORE SKILLS:

VHDL synthesis: Xilinx XST, Exemplar LeonardoSpectrum, Sinplicity Synplify, Synopsys FPGA Express;
P&R: Xilinx ISE, Xilinx Foundation Express, Altera MAX+plusII;
RTL / postP&R simulation: ModelSim, ChipScope Pro;
FPGA/PLD families: Spartan6, Spartan3(AN), Spartan2, XC4000XL, XC9500XL, MAX7000
Hardware PCB design: Altium Designer, P-CAD, OrCAD;
Hardware design simulation: MicroCap, ElectronicWorkbench;

$10 / Hour
$200 minimum budget

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