Use to develop on the CAD Flow Methodologies as per the Circuit Designer Team requirements and as per Assembly guidelines and Manufacturer Important Knowledge and Task in Layout Activities PCB Layout Done High Speed from 4-6.4GBPS Library Managements of Altera, Xilinx and Test Chips of 1156 Pins and Pin Mapping for the Programmable FPGA’s Part Mapping and Footprint Creation in Concept HDL and Cadence-Allegro, Mentor Graphics - PADS and Zuken Cad star Worked more than 4000 Parts for mapping in library development Worked on R+LPDDR, Scan interface and USB lim and Eagle2 Revision Cards Worked on Blind and Buried Vias using ISOLA as a Di-electric and laser Vias Technologies Worked on Metal Core and thermal Core Projects. Worked on industrial and Automotive, RF, DDRS and commercial Boards Checklist and Documentation Maintaining DFM/DFA issues solving