Designed and implemented DSP software equalizers, tone detectors, correlation detectors, and timing recovery algorithms for central- office (CO) symmetric DSL modems compliant to Annex C and H standards.
Worked on DSP software frequency-domain equalizer and constellation decoder for Annex A Integrated Access Device (IAD). Provided support for interoperability issues from the field.
Developed, implemented, and characterized buffer management algorithms to manage traffic between a proprietary ADSL chip and the USB or PCI bus.
Designed and implemented ANSI handshaking algorithms for Annex A (U.S.) DSL modems.
Developed and simulated phase-tracking loops, Viterbi decoder, and scrambling algorithms for a spread-spectrum satellite using Matlab and C.
Wrote algorithms in C and assembly for the TMS320C4x and TMS320C6x DSPs.
Designed an FPGA (100,000 gates) using Verilog HDL and Synplicity.
Modeled an FIR pul