RTL, ASIC Frond-End Design, FPGA Design (3805518)

Engineering & Architecture

RTL, ASIC Frond-End Design, FPGA Design

$35/hr Starting at $25

I have about four-year experience of ASIC Frond-End Design. My main project is for PCIe Interface. Because I have this experience, I can develop good quality design. I can finish this item as followed: 1. ASIC Front-End, STA 2. SPI, Uart interface 3. FPGA Verification and use Xilinx Zynq to have a turkey solution. 4. Assist to develop big-data algorithm by building a hardware platform.

About

$35/hr Ongoing

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I have about four-year experience of ASIC Frond-End Design. My main project is for PCIe Interface. Because I have this experience, I can develop good quality design. I can finish this item as followed: 1. ASIC Front-End, STA 2. SPI, Uart interface 3. FPGA Verification and use Xilinx Zynq to have a turkey solution. 4. Assist to develop big-data algorithm by building a hardware platform.

Skills & Expertise

DesignFPGARtl

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