I have completed my Bachelor's degree from Carlos III University from Madrid (Spain) in Industrial Engineering and finishing my Master's degree in Advanced Electronics Presently I am working with INDRA SISTEMAS SA from the last years as a digital hardware designer. Throughout my career I have acquired a very good knowledge of FPGA design technologies and embedded processors. Because of my investigation at the University in Single Event Transient Faults in ASIC, I have strong knowledge in FPGA and ASIC timing with a BEST PAPER AWARD at DFT 2007 in the Fault Tolerance Area.