$5/hr
                                                            ·
                                                            
                                                            Starting at
                                                            $25
                                                            
                                                            
                                                              Ongoing
                                                            
                                                            
                                                        
                                                        
                                                        ASIC/IC Design flow: - executable specifications/behavioral model - RTL design and verification with Verilog/VHDL,  - CAD setup and configuration, project database - Synthesis/Timing analysis (Synopsys...
                                                        
                                                        
                                                            AlgorithmsC Programming LanguageC++CADDebugging