A highly motivated Digital IC Design Engineer with expertise in Verilog, SystemVerilog, and VHDL for complex RTL design. a strong background in Computer Architecture, specializing in MIPS architectures (pipelining, hazard handling, and memory hierarchies) and Digital Signal Processing. I have a deep understanding of industry-communication protocols, including AMBA, UART, SPI, and I2C alongside hands-on proficiency in STA, CDC, DFT and low-power design techniques.
Beyond front-end design, I'm also expertise in the physical design (floorplanning, power planning, placement, CTS, routing, DRC/LVS, etc.)
EDA Tools: Synopsys (Design Compiler, ICC2, PrimeTime, SpyGlass, Formality), Xilinx Vivado, Intel Quartus prime, QuestaSim