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Skills

  • Design
  • FPGA
  • SystemVerilog
  • Verilog
  • VHDL
  • Vivado

Services

  • Design and front-end verification

    $9/hr Starting at $25 Ongoing

    Dedicated Resource

    To design and verify the design using HDLs like verilog, VHDL and SystemVerilog using QuestaSim. Work on FPGA using Vivado.

    DesignFPGASystemVerilogVerilogVHDL

About

Interested to work in VLSI domain.

Completed 45 days HEP training at Mentor Graphics, Bangalore based on digital design and verification using SystemVerilog.

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Designers

FPGA Developers