Above and beyond
20 years of hands-on industry experience in both ASIC and FPGA design flow.
Strong track record of design high speed serial communication interface like USB/PCIe/ xPON/XAUI/XGE physical layer and link layer module Framer/ PHY/MAC/PCS with 2.5G/10G SerDes from industry standard to mass-production products.
Proven capability of hardware system development process in full life-cycle including requirement gathering, architect, micro-architect, RTL coding, SOC integration, STA, ECO, formal verification, silicon bring up, and multi-site cross functional team support.
Expertise in telecom network switching and routing, data encryption and authentication, error correction code, computer architecture memory and cache interface, and DSP FIR/IIR.
Pending patent US 20090172675 A1 for atomic process context switch.
Work Terms
TBD but guarantee to provide at least 20 hours per week