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Skills

  • Design Verification Testing
  • Uvm
  • Verilog

Services

  • Frontend Design and Verify engineer

    $8/hr Starting at $25 Ongoing

    Dedicated Resource

    I'm an 5-year experience frontend engineer in design and verify. worked in more than 10 projects with Memory controller, PHY, DLL, BIST design and verification

    Design Verification TestingUvmVerilog