8 Years of experience in Full custom layout Design including Analog and mixed signal layout and IO cells ? Layout Design experience in different process technologies like7nm Finfet, 16nm Finfet, 10nmFinfet, 28nm, 40nm, 130nm SOI process, 180nm and 350nm etc. ? Good fundamental understanding of CMOS basics, Basic Circuit Analysis, Layout Concepts, Methods and Fabrication Process. ? Good knowledge and work experience on deep sub-micron technologies and advanced process improvements such as double patterning. ? Experienced in floor planning, placement and routing of macro blocks. ? Well Aware of Matching and shielding techniques in Analog layout and also how to handle long term and short-term failures like EM, Latch up, Antenna and ESD. ? Experienced in Cadence Virtuoso L, XL & GXL, Auotouter, Digital Placement planning, Digital placer, Calibre, Assura & PVS. ? Knowledge of Physical verification including run file creation, strong debug and problem-solving skill for LVS/DRC/ERC antenna and layout issues, Density Checks and fills. And also, Reliability verification and fixes. ? Knowledge on Tool development and validation like CSR (cadence space-based router), Autorouter, Constraint Manager & ICC2 toll for placement for routing of digital blocks. ? Good Knowledge on skill scripting.