Design Verification using V_SV_UVM_Perl.

Programming & Development Programming & Software

$12/hr Starting at $30

I have 7 years in Design verification using Verilog, Systemverilog and UVM.

with Perl Automation. I can deliver code of verification components alongwith assertions and coverage model.

provided the specification of the design. The methodology will be UVM and tool will be QuestaSim.

Complete documentation will be provided alongwith.

$12/hr Ongoing

I have 7 years in Design verification using Verilog, Systemverilog and UVM.

with Perl Automation. I can deliver code of verification components alongwith assertions and coverage model.

provided the specification of the design. The methodology will be UVM and tool will be QuestaSim.

Complete documentation will be provided alongwith.

Design Verification TestingLinuxPerlSystemVerilogVerilog

Sunil Sharma 103