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Skills

  • Design Verification Testing
  • Linux
  • Perl
  • SystemVerilog
  • Verilog

Services

  • Design Verification using V_SV_UVM_Perl.

    $12/hr Starting at $30 Ongoing

    Dedicated Resource

    I have 7 years in Design verification using Verilog, Systemverilog and UVM. with Perl Automation. I can deliver code of verification components alongwith assertions and coverage model. provided the specification...

    Design Verification TestingLinuxPerlSystemVerilogVerilog

About

I have 7 years of workex in Design Verification using SystemVerilog and UVM. I can deliver the Verification code and can teach programming languages like C/C++/Verilog/SystemVerilog etc.

I am Sunil Sharma, from India. I like to write code in Design and Verification languages like Verilog, Systemverilog and UVM.
I like to explore the optimisation techniques of coding especially in systemverilog and UVM.
My hobbies include cooking, playing sports, yoga, meditation and walking. I also like to teach various programming languages like C/C++/Verilog and SystemVerilog.

Work Terms

You can decide the complete project amount.

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