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Digital IP Design for ASIC & FPGA

**About Me** I have 20+ years of experience in ASIC/FPGA Design. While RTL coding (Verilog & VHDL), verification(Verilog,Cocotb), Synthesis and timing closure is my core skill, I have also worked extensively on Firmware and Device driver development for my designs. As a highly skilled engineer, I have been working with client's and projects across multiple domains and have provided solutions for * Networking(Switches, Ethernet, WLAN, Docsis), **Typical Project Workflow** I normally engage with clients on long term multi-month, multi year projects. The Client engagement is spread over the following Milestones. ML1: Project discussion and planning. This phase is a series of discussion over phone, IM, email etc. This phase is for knowledge sharing and to arrive at a common understanding of the Project goals. At the end of this phase we should have 1. A statement of work, **ML2--ML6 RTL Coding and Verification** The development phase is split across multiple milestones. While the exact milestones depend of the project and client, they more or less fall in the following category. ML2: Initial RTL and verification environment are integrated and compile. ML7-ML9: Synthesis, TIming closure and handover to the backend team. ML10 Post Silicon support. If your are interested and want to discuss further, drop me a message and I will respond within a day or two.

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$40/hr Ongoing

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**About Me** I have 20+ years of experience in ASIC/FPGA Design. While RTL coding (Verilog & VHDL), verification(Verilog,Cocotb), Synthesis and timing closure is my core skill, I have also worked extensively on Firmware and Device driver development for my designs. As a highly skilled engineer, I have been working with client's and projects across multiple domains and have provided solutions for * Networking(Switches, Ethernet, WLAN, Docsis), **Typical Project Workflow** I normally engage with clients on long term multi-month, multi year projects. The Client engagement is spread over the following Milestones. ML1: Project discussion and planning. This phase is a series of discussion over phone, IM, email etc. This phase is for knowledge sharing and to arrive at a common understanding of the Project goals. At the end of this phase we should have 1. A statement of work, **ML2--ML6 RTL Coding and Verification** The development phase is split across multiple milestones. While the exact milestones depend of the project and client, they more or less fall in the following category. ML2: Initial RTL and verification environment are integrated and compile. ML7-ML9: Synthesis, TIming closure and handover to the backend team. ML10 Post Silicon support. If your are interested and want to discuss further, drop me a message and I will respond within a day or two.

Skills & Expertise

EmbeddedFPGAVerilogVHDLVLSI

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