Bengaluru, Karnataka, India
$6/hr · Starting at $25
I am ASIC verification engineer with 5.5+ years experience. Extensive knowledge .PCIe Gen5/4/3/2/1 Protocol and PIPE 4.4.1. Expertise in UVM, verilog, system verilog , System verilog Assertion, shell…
Thane, Maharashtra, India
$8/hr · Starting at $25
ASIC verification Engineer with support till desired verification goal reached . I am highly target driven and always go to extra mile to achieve client complete satisfaction.
San Gregorio, California, United States
$100/hr · Starting at $500
VLSI, SoC Verification, ASIC Verification, UVM, System Verilog, Veriolg, C/C++, Perl, Python, Linux, Functional Coverages, System Verilog Assertions, ACE, AXI, AHB, APB, I2C, SPI, JTAG TAP, 8b/10b Enc…
Kochi, Kerala, India
$25/hr · Starting at $600
I can take up work in ASIC,VLSI domain starting with micro architecture design, Verilog/VHDL RTL design, Lint and CDC tasks for RTL FPGA design, Embedded system hardware design or developing schemati…
seongnam, Kyonggi-do, South Korea
$35/hr · Starting at $25
I am an ASIC designer specially digital logic by verilog. I had worked world Top ranked semi company 10 years. Major field is IP design for interface and Testchip for verification of IP. I worked f…
$5/hr · Starting at $25
I have 2 years of industrial experience in ASIC design & verification, I have good hands on experience in protocols, developed uvm n sv verification environment from scratch, can work on scripting as
Lahore, Punjab, Pakistan
$20/hr · Starting at $50
Digital Systems Design or Embedded Systems Projects. Verilog and VHDL design, testing and verification including test benches, Arduino Programming, Microcontrollers and microprocessor projects. Cadenc…
Mississauga, Ontario, Canada
ID Verified
$24/hr · Starting at $200
FPGA and ASIC front end design, Verilog and SystemVerilog IP cores design and verification. FPGA based embedded system design and full cycle implementation
Nashik, Maharashtra, India
FPGA IC design projects using ALTERA Qurtus II, NIOS II processor, SOPC Builder, Modelsim using licensed version of the tool. Also Semi custom ASIC IC Design from RTL to GDS2 using Cadence SoC encount…
Taipei, T'ai-pei, Taiwan
I have about four-year experience of ASIC Frond-End Design. My main project is for PCIe Interface. Because I have this experience, I can develop good quality design. I can finish this item as follow…
Bhubaneswar, Odisha, India
Writing testcases in sv using UVM , worked on ZEBU tool verification. debug testcases for PCIE, have sound knowledge on verilog
Visnagar, Gujarat, India
Hello , I have done my Post Graduation in VLSI System Design and have undergone a 6 months training in ASIC Physical Design Domain. So having good programming knowledge in Perl, SHELL Scripting , Veri…
San Jose, California, United States
$75/hr · Starting at $300
12+ years of industry experience in all aspects of VLSI design and implementation Timing signoff for 20+ tapeouts on sub micron nodes with various fabs Expertise in constraints debug, timing signoff,
Mumbai, Maharashtra, India
$10/hr · Starting at $100
having 7 years of experience in relevant field. completed 8 projects in analog mixed signal ic design layout field and pcb layout design field.
Chennai, Tamil Nadu, India
$10/hr · Starting at $30
I have 7 years of experience in EDA chip design and verification.I am working with the languages verilog,system verilog and OVM ,UVM
Madison, Wisconsin, United States
5 years of industry experience in SOC Verification. Self motivated, quick learner with enthusiasm to learn and expand knowledge. Skills/Strengths: Languages : Verilog , System Verilog , C, C++. Script…
Ahmedabad, Gujarat, India
I am having industry working experience of 4+ years. I have extensive knowledge in C, C++, Java, Verilog and System Verilog. I am a Oracle Certified java professional. I am looking for part time proj…
$90/hr · Starting at $1,000
20+ hands on experience working on ASIC and FPGA design and implementation from algorithms to tape out
Ho Chi Minh, Ho Chi Minh, Vietnam
$30/hr · Starting at $40
- Responsible for the the physical design from RTL to GDSII, hardening the high speed digital blocks such as DDR PHY, Serializer. - Working closely with RTL designer to develop the SDC and related req…
Yerevan, Yerevan, Armenia
$20/hr · Starting at $25
Digital Front-End Designing. Write RTL in verilog, verification. Work: Have 8+ years experience in Digital Design. Education: MSC and BSC of VLSI design design/architecture development per specificati…